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Freescale Semiconductor, Inc.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number: MM908E625 Rev 3.0, 09/2004
Advance Information Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication
The 908E625 is an integrated single-package solution that includes a highperformance HC08 microcontroller with a SMARTMOS TM analog control IC. The HC08 includes flash memory, a timer, enhanced serial communications interface (ESCI), an analog-to-digital converter (ADC), serial peripheral interface (SPI), and an internal clock generator (ICG) module. The analog control die provides fully protected H-Bridge/high-side outputs, voltage regulator, autonomous watchdog with cyclic wake-up, and local interconnect network (LIN) physical layer. The single-package solution, together with LIN, provides optimal application performance adjustments and space-saving PCB design. It is well suited for the control of automotive mirror, door lock, and light-levelling applications. Features * High-Performance M68HC08EY16 Core * 16 K Bytes of On-Chip Flash Memory * 512 Bytes of RAM * Internal Clock Generation Module * Two 16-Bit, 2-Channel Timers * 10-Bit Analog-to-Digital Converter * Three 2-Terminal Hall-Effect Sensor Input Ports * One Analog Input with Switchable Current Source * Four Low RDS(ON) Half-Bridge Outputs * One Low RDS(ON) High-Side Output * 13 Microcontroller I/Os 908E625 Simplified Application Diagram Simplified Application Diagram
908E625 908E625 LIN VREFH VDDA EVDD VDD VREFL VSSA EVSS VSS RST RST_A IRQ IRQ_A SS PTB1/AD1 RXD PTE1/RXD PTD1/TACH1 FGEN BEMF PTD0/TACH0/BEMF VSUP[1:3] HB1 M HB2 HB3 HB4 HS High-Side Output HVDD H1 H2 H3 PA1 Port A I/Os Port B I/Os Port C I/Os Switchable Internal VDD Output M M
908E625
H-BRIDGE POWER SUPPLY WITH EMBEDDED MCU AND LIN
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DWB SUFFIX CASE 1400-01 54-TERMINAL SOICWB-EP
ORDERING INFORMATION
Device MM908E625ACDWB/R2 Temperature Range (TA) -40C to 85C Package 54 SOIC WB-EP
4 Half-Bridges Controlling 3 Loads
Three 2-Terminal Hall-Effect Sensor Inputs Analog Input with Current Source Microcontroller Ports
GND[1:2] EP
This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Motorola, Inc. 2004
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PTD0/TACH0 PTB1/AD1 VSUP1-3
CPU Registers ALU 5-Bit Keyboard Interrupt Module
Internal Bus
DDRC
DDRA
PORT A
PTC3/OSC2
PTD1/TACH1 PTD0/TACH0
PORT C
DDRD
PORT D
PORT B
DDRB
DDRE
PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTE1/RxD PTE0/TxD PORT E
908E625 2
GND1-2 RST_A IRQ_A FGEN BEMF SS PTD1/TACH1 PTE1/RXD VREFL EVDD EVSS VSSA RXD RST LIN IRQ
Single Breakpoint Break Module Voltage Regulator
VREFH VSS VDD PTE0/TXD TXD
LIN Physical Layer 2-Channel Timer Interface Module A Reset Control Module 2-channel Timer Interface Module B
FGEN VSUP
Control and Status Register, 64 Bytes
VDDA
Switched VDD Driver & Diagnostic
M68HC08 CPU
User Flash, 15,872 Bytes
User RAM, 512 Bytes
Monitor ROM, 310 Bytes
HVDD
PTA0/KBD0
Enhanced Serial Communication Interface Module Computer Operating Properly Module Interrupt Control Module
Flash Programming (burn in) ROM, 1024 Bytes
PTA1/KBD1
Internal Clock Generator Module
User Flash Vector Space, 36 Bytes
High Side Driver & Diagnostic
HS
VSUP FGEN
OSC2 OSC1
PTA2/KBD2 SS
24 Internal System Integration Module Serial Pheripheral Interface Module
PTA3/KBD3 PTC0/MISO PTC1/MOSI MOSI SPSCK PTA5/SPSCK MISO
Single External IRQ Module Configuration Register Module
RST
BEMF
Half Bridge Driver & Diagnostic
HB1
PTA4/KBD4
IRQ
VSUP FGEN
SPI & CONTROL
PTB3/AD3
10 Bit Analog-toDigital Converter Module Periodic Wake-Up Timebase Module
PTB4/AD4
POWER Arbiter Module
VREFH VDDA VREFL VSSA
BEMF
Half Bridge Driver & Diagnostic
VSUP FGEN
HB2
PTB5/AD5
Power-On Reset Module Prescaler Module
VDD VSS
PTB6/AD6/TBCH0
BEMF
Half Bridge Driver & Diagnostic Autonomous Watchdog
VSUP FGEN
HB3
PTB7/AD7/TBCH1
Security Module BEMF Module
PTC2/MCLK
PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTC1/MOSI PTC0/MISO
Chip Temp
BEMF
Figure 1. 908E625 Simplified Internal Block Diagram
HB4
VSUP Prescaler
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PTA6/SS PTA5/SPSCK PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0
Half Bridge Driver & Diagnostic
H1 PTB0/AD0 ADOUT
Hall-Effect Sensor Inputs Analog Multiplexer
PTC4/OSC1
H2 H3
Analog Input with Current Source
FLSVPP
MCU Die
Analog Die
PA1
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Figure 1. 908E625 Simplified Internal Block Diagram
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Transparent Top View of Package
PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK PTB5/AD5 PTB4/AD4 PTB3/AD3
IRQ RST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42
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PTB1/AD1 PTD0/TACH0/BEMF PTD1/TACH1 NC FGEN BEMF
RST_A IRQ_A SS
Exposed Pad
41 40 39 38 37 36 35 34 33 32 31 30 29 28
LIN NC NC HB1 VSUP1 GND1 HB2 VSUP2
PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 FLSVPP PTA3/KBD3 PTA4/KBD4 VREFH VDDA EVDD EVSS VSSA VREFL PTE1/RXD RXD VSS PA1 VDD H1 H2 H3 HVDD NC HB4 VSUP3 GND2 HB3 HS
TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section beginning on page 15.
Die MCU Terminal 1 2 6 7 8 11 3 4 5 9 10 12 13 14, 21, 22, 33 42 43 48 44 47 Terminal Name PTB7/AD7/TBCH1 PTB6/AD6/TBCH0 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB1/AD1 PTC4/OSC1 PTC3/OSC2 PTC2/MCLK
IRQ RST
Formal Name Port B I/Os
Definition These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU.
MCU
Port C I/Os
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. This terminal is an asynchronous external interrupt input terminal. This terminal is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. Not connected. This terminal is a special-function, bidirectional I/O port terminal that can is shared with other functional modules in the MCU. These terminals are the reference voltage terminals for the analog-todigital converter (ADC). These terminals are the power supply terminals for the analog-to-digital converter.
MCU MCU MCU - MCU MCU MCU
External Interrupt Input External Reset Port D I/Os No Connect Port E I/O ADC References ADC Supply Terminals
PTD0/TACH0/BEMF PTD1/TACH1 NC PTE1/RXD VREFL VREFH VSSA VDDA
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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TERMINAL DEFINITIONS (continued) A functional description of each terminal can be found in the System/Application Information section beginning on page 15.
Die MCU MCU Terminal 45 46 49 50 52 53 54 51 15 16 17 18 19 20 23 26 29 32 24 27 31 25 30 28 34 Terminal Name EVSS EVDD PTA4/KBD4 PTA3/KBD3 PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 FLSVPP FGEN BEMF Formal Name MCU Power Supply Terminals Port A I/Os Definition These terminals are the ground and power supply terminals, respectively. The MCU operates from a single power supply. These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU.
MCU Analog
Test Terminal Current Limitation Frequency Input Back Electromagnetic Force Output Internal Reset Internal Interrupt Output Slave Select LIN Bus Half-Bridge Outputs
For test purposes only. Do not connect in the application. This is the input terminal for the half-bridge current limitation and the highside inrush current limiter PWM frequency. This terminal gives the user information about back electromagnetic force (BEMF). This terminal is the bidirectional reset terminal of the analog die. This terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. This terminal is the SPI slave select terminal for the analog chip. This terminal represents the single-wire bus transmitter and receiver. This device includes power MOSFETs configured as four half-bridge driver outputs. These outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. These terminals are device power supply terminals.
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Analog Analog Analog Analog Analog Analog
RST_A IRQ_A
SS
LIN HB1 HB2 HB3 HB4 VSUP1 VSUP2 VSUP3 GND1 GND2 HS HVDD
Analog
Power Supply Terminals Power Ground Terminals High-Side Output Switchable VDD Output Hall-Effect Sensor Inputs Voltage Regulator Output Analog Input Voltage Regulator Ground LIN Transceiver Output Exposed Pad
Analog Analog Analog
These terminals are device power ground connections. This output terminal is a low RDS(ON) high-side switch. This terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors. These terminals provide inputs for Hall-effect sensors and switches.
Analog
35 36 37 38 39 40 41 EP
H3 H2 H1 VDD PA1 VSS RXD Exposed Pad
Analog Analog Analog Analog -
The +5.0 V voltage regulator output terminal is intended to supply the embedded microcontroller. This terminal is an analog input port with selectable source values. Ground terminal for the connection of all non-power ground connections (microcontroller and sensors). This terminal is the output of LIN transceiver. The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board.
908E625 4
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to the device.
Rating Symbol Value Unit
ELECTRICAL RATINGS
Supply Voltage Analog Chip Supply Voltage under Normal Operation (Steady-State) Analog Chip Supply Voltage under Transient Conditions (Note 1) Microcontroller Chip Supply Voltage Input Terminal Voltage Analog Chip Microcontroller Chip VIN(ANALOG) VIN(MCU) IPIN(1) IPIN(2) IMVSS IMVDD -0.3 to 5.5 VSS -0.3 to VDD +0.3 mA 15 25 100 100 mA mA V VBUS(SS) VBUS(DYNAMIC) VESD1 VESD2 VESD3 -18 to 28 40 V 3000 150 500 VSUP(SS) VSUP(PK) VDD -0.3 to 28 -0.3 to 40 -0.3 to 6.0 V V
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Maximum Microcontroller Current per Terminal All Terminals Except VDD, VSS, PTA0:PTA6, PTC0:PTC1 Terminals PTA0:PTA6, PTC0:PTC1 Maximum Microcontroller VSS Output Current Maximum Microcontroller VDD Input Current LIN Supply Voltage Normal Operation (Steady-State) Transient Conditions (Note 1) ESD Voltage Human Body Model (Note 2) Machine Model (Note 3) Charge Device Model (Note 4)
THERMAL RATINGS
Storage Temperature Operating Case Temperature (Note 5) Operating Junction Temperature Analog MCU Terminal Soldering Temperature (Note 6) Thermal Resistance (Junction to Ambient) All Outputs ON (Note 7), (Note 9) Single Output ON (Note 8), (Note 9) RJA1 RJA2 24 27 TJ(ANALOG) TJ(MCU) TSOLDER -40 to 150 -40 to 125 245 C C/W TSTG TC -40 to 150 -40 to 85 C C C
Notes 1. Transient capability for pulses with a time of t < 0.5 sec. 2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). 3. 4. 5. 6. 7. 8. 9. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP = 0 ). ESD3 testing is performed in accordance with Charge Device Model, robotic (CZAP =4.0 pF). The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. All outputs ON and dissipating equal power. One output ON and dissipating power. Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7 and JESD51-5 (thermal vias connected to top ground plane).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SUPPLY VOLTAGE
Nominal Operating Voltage VSUP 8.0 - 18 V
SUPPLY CURRENT
NORMAL Mode VSUP = 12 V, Power Die ON (PSON=1), MCU Operating Using Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled IRUN - ISTOP - - 60 20 - A mA
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STOP Mode (Note 10) VSUP = 12 V, Cyclic Wake-Up Disabled
DIGITAL INTERFACE RATINGS (ANALOG DIE)
Output Terminals RST_A, IRQ_A Low-State Output Voltage (IOUT = -1.5 mA) High-State Output Voltage (IOUT = 1.0 A) Output Terminals BEMF, RXD Low-State Output Voltage (IOUT = -1.5 mA) High-State Output Voltage (IOUT = 1.5 mA) Output Terminal RXD-Capacitance (Note 11) Input Terminals RST_A, FGEN, SS Input Logic Low Voltage Input Logic High Voltage Input Terminals RST_A, FGEN, SS-Capacitance (Note 11) Terminals RST_A, IRQ_A-Pullup Resistor Terminal SS-Pullup Resistor Terminals FGEN, MOSI, SPSCK-Pulldown Resistor Terminal TXD-Pullup Current Source Notes 10. STOP mode current will increase if VSUP exceeds 15 V. 11. This parameter is guaranteed by process monitoring but is not production tested. VIL VIH CIN RPULLUP1 RPULLUP2 RPULLDOWN IPULLUP - 3.5 - - - - - - - 4.0 10 60 60 35 1.5 - - - - - - pF k k k A VOL VOH CIN - 3.85 - - - 4.0 0.4 - - pF V VOL VOH - 3.85 - - 0.4 - V V
908E625 6
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
SYSTEM RESETS AND INTERRUPTS
High-Voltage Reset Threshold Hysteresis Low-Voltage Reset Threshold Hysteresis VLVRON VLVRH VHVION VHVIH VLVION VLVIH TRON TRH TION TIH 3.6 - 4.0 100 4.5 - V mV V 17.5 - 21 1.0 23 - V 6.5 - - 0.4 8.0 - VHVRON VHVRH 27 - 30 1.5 33 - V
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High-Voltage Interrupt Threshold Hysteresis Low-Voltage Interrupt Threshold Hysteresis High-Temperature Reset (Note 12) Threshold Hysteresis High-Temperature Interrupt (Note 13) Threshold Hysteresis - 5.0 160 - - - - 5.0 170 - - -
C
C
VOLTAGE REGULATOR
Normal Mode Output Voltage IOUT = 60 mA, 6.0 V < VSUP < 18 V Load Regulation IOUT = 80 mA, VSUP = 9.0 V, TJ = 125C STOP Mode Output Voltage (Maximum Output Current 100 A) VDDSTOP VLR - 4.5 - 4.7 100 4.9 V VDDRUN 4.75 5.0 5.25 mV V
Notes 12. This parameter is guaranteed by process monitoring but is not production tested. 13. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10C).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN PHYSICAL LAYER
Output Low Level TXD LOW, 500 Pullup to VSUP Output High Level TXD HIGH, IOUT = 1.0 A Pullup Resistor to VSUP RSLAVE IBUS_PAS_rec 0 - 20 A IBUS_NO_GND IBUS - - -600 25 - - V VIH VIL VITH VIHY VWTH 0.6 VLIN 0 - 0.01 VSUP - - - VSUP /2 - VSUP /2 VSUP 0.4 VLIN - 0.1 VSUP - V VLIN-HIGH VSUP -1.0 20 - 30 - 60 k A VLIN-LOW - - 1.4 V V
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Leakage Current to GND Recessive State (-0.5 V < VLIN < VSUP) Leakage Current to GND (VSUP Disconnected) Including Internal Pullup Resistor, VLIN @ -18 V Including Internal Pullup Resistor, VLIN @ +18 V LIN Receiver Recessive Dominant Threshold Input Hysteresis LIN Wake-Up Threshold
HIGH-SIDE OUTPUT (HS)
Switch ON Resistance @ TJ = 25C with ILOAD = 1.0 A High-Side Overcurrent Shutdown RDS(ON)HS IHSOC - 3.9 600 - 700 7.0 m A
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
HALF-BRIDGE OUTPUTS (H1:H4)
Switch ON Resistance @ TJ = 25C with ILOAD = 1.0 A High Side Low Side High-Side Overcurrent Shutdown Low-Side Overcurrent Shutdown RDS(ON)HB_HS RDS(ON)HB_LS - - 4.0 3.5 425 400 - - 500 500 7.5 7.5 m
IHBHSOC IHBLSOC
ICL1 ICL2 ICL3 ICL4 ICL5 VBEMFH VBEMFL VBEMFHY RATIOH RATIOL
A A
mA
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Low-Side Current Limitation @ TJ = 25C Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1) Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0) Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1) Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0) Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1) Half-Bridge Output HIGH Threshold for BEMF Detection Half-Bridge Output LOW Threshold for BEMF Detection Hysteresis for BEMF Detection Low-Side Current-to-Voltage Ratio (VADOUT [V]/IHB [A]) CSA = 1 CSA = 0
- 210 300 450 600 - - -
55 260 370 550 740 -30 -60 30
- 315 440 650 880 0 -5.0 - V mV mV V/A
7.0 1.0
12.0 2.0
14.0 3.0
SWITCHABLE VDD OUTPUT (HVDD)
Overcurrent Shutdown Threshold IHVDDOCT 24 30 40 mA
VSUP DOWN-SCALER
Voltage Ratio (RATIOVSUP = VSUP /VADOUT) RATIOVSUP 4.8 5.1 5.35 -
INTERNAL DIE TEMPERATURE SENSOR
Voltage/Temperature Slope Output Voltage @ 25C STtoV VT25 - 1.7 19 2.1 - 2.5 mV/C V
HALL-EFFECT SENSOR INPUTS (H1:H3)
Output Voltage VSUP < 16.2 V VSUP > 16.2 V Sense Current Threshold Hysteresis Output Current Limitation Overcurrent Warning HP_OCF Flag Threshold] Dropout Voltage @ ILOAD = 15 mA IHSCT IHSCH 6.9 - - - - 8.8 0.88 90 3.0 0.5 11 - - - - mA V V VHALL1 VHALL2 - - VSUP -1.2 - - 15 mA V
IHL
VHPOCT VHPDO
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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STATIC ELECTRICAL CHARACTERISTICS (continued) All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
ANALOG INPUT (PA1)
Current Source PA1 CSSEL1 = 1, CSSEL0 = 1 Selectable Scaling Factor Current Source PA1 (I(N) = ICSPA1* N) CSSEL1 = 0, CSSEL0 = 0 CSSEL1 = 0, CSSEL0 = 1 CSSEL1 = 1, CSSEL0 = 0 ICSPA1 570 670 770 % NCSPA1-0 NCSPA1-1 NCSPA1-2 8.5 28.5 58.5 10 30 60 11.5 31.5 61.5 A
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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DYNAMIC ELECTRICAL CHARACTERISTICS All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40C TJ 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
LIN PHYSICAL LAYER
Propagation Delay (Note 14), (Note 15) TXD LOW to LIN LOW TXD HIGH to LIN HIGH LIN LOW to RXD LOW LIN HIGH to RXD HIGH TXD Symmetry t TXD-LIN-low t TXD-LIN-high t LIN-RXD-low t LIN-RXD-high t TXD-SYM t RXD-SYM SRF -1.0 SRR 1.0 SRS -2.0 2.0 - 3.0 2.0 s -2.0 -3.0 V/s - - - - -2.0 -2.0 - - 4.0 4.0 - - 6.0 6.0 8.0 8.0 2.0 2.0 V/s s
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RXD Symmetry Output Falling Edge Slew Rate (Note 14), (Note 16) 80% to 20% Output Rising Edge Slew Rate (Note 14), (Note 16) 20% to 80%, RBUS > 1.0 k, CBUS < 10 nF LIN Rise/Fall Slew Rate Symmetry (Note 14), (Note 16)
HALL-EFFECT SENSOR INPUTS (H1:H3)
Propagation Delay t HPPD - 1.0 - s
AUTONOMOUS WATCHDOG (AWD)
AWD Oscillator Period AWD Period Low = 512 t OSC AWD Period High = 256 t OSC AWD Cyclic Wake-Up On Time t OSC t AWDPH t AWDPL t AWDHPON - 16 8.0 - 40 22 11 90 - 28 14 - s ms ms s
Notes 14. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0:SRS1= 00). 15. See Figure 2, page 11. 16. See Figure 3, page 11.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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.
MICROCONTROLLER For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Module Core Timer Flash RAM ADC SPI ESCI Description High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz Two 16-Bit Timers with Two Channels (TIM A and TIM B) 16 K Bytes 512 Bytes 10-Bit Analog-to-Digital Converter SPI Module Standard Serial Communication Interface (SCI) Module Bit-Time Measurement Arbitration Prescaler with Fine Baud-Rate Adjustment Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%) Special Counter for SMARTMOS BEMF Output
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ICG BEMF Counter
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Timing Diagrams
t TXD-LIN-low t
Tx-LIN-low
t TXD-LIN-high tTx-LIN-high
TXD Tx TXD
LIN LIN
Recessive State
0.9 VSUP 0.9 VSUP
Recessive State
0.6 VSUP VSUP
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0.4 VSUP VSUP
0.1 VSUP 0.1 VSUP
Dominant State
Rx RXD
t LIN-RXD-low t
LIN-Rx-low
t LIN-RXD-high t
LIN-Rx-high
Figure 2. LIN Timing Description
t Fall-time
t Rise-time
0.8 VSUP 0.8 VSUP
0.8 VSUP VSUP
V Fall
V Rise
0.2 VSUP 0.2 VSUP
Dominant State
0.2 VSUP 0.2 VSUP
SRF =
V Fall t Fall-time
SRR =
V Rise t Rise-time
Figure 3. LIN Slew Rate Description
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Functional Diagrams
1.6 1.4 1.2 1.0 TJ = 25C
Volts
Volts
0.8 0.6 0.4
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0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Amperes Amperes H-Bridge Low Side
Figure 4. Free Wheel Diode Forward Voltage
250
200 TA = 125C
Dropout (mV) Drop Out (mV)
150
100
TA = 25C
50
TA = -40C
0 0 5 5.0 10
IILoad (mA) LOAD (mA)
15
20
25
Figure 5. Dropout Voltage on HVDD
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 908E625 device was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. For automotive body electronics, the 908E625 is well suited to perform complete mirror, door lock, and light-levelling control all via a 3-wire LIN bus. This device combines an standard HC08 MCU core (68HC908EY16) with flash memory together with a SMARTMOS IC chip. The SMARTMOS IC chip combines power and control in one chip. Power switches are provided on the SMARTMOS IC configured as half-bridge outputs with one high-side switch. Other ports are also provided; they include Hall-effect sensor input ports, analog input ports, and a selectable HVDD terminal. An internal voltage regulator is provided on the SMARTMOS IC chip, which provides power to the MCU chip. Also included in this device is a LIN physical layer, which communicates using a single wire. This enables the device to be compatible with 3-wire bus systems, where one wire is used for communication, one for battery, and the third for ground.
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FUNCTIONAL TERMINAL DESCRIPTION
See Figure 1, 908E625 Simplified Internal Block Diagram, page 2, for a graphic representation of the various terminals referred to in the following paragraphs. Also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package.
Port D I/O Terminals
PTD1/TACH1 and PTD0/TACH0/BEMF are specialfunction, bidirectional I/O port terminals that can also be programmed to be timer terminals. In step motor applications the PTD0 terminal should be connected to the BEMF output of the analog die in order to evaluate the BEMF signal with a special BEMF module of the MCU. PTD1 terminal is recommended for use as an output terminal for generating the FGEN signal (PWM signal) if required by the application.
Port A I/O Terminals
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. PTA0:PTA4 are shared with the keyboard interrupt terminals, KBD0:KBD4. The PTA5/SPSCK terminal is not accessible in this device and is internally connected to the SPI clock terminal of the analog die. The PTA6/SS terminal is likewise not accessible. For details refer to the 68HC908EY16 datasheet.
Port E I/O Terminal
PTE1/RXD and PTE0/TXD are special-function, bidirectional I/O port terminals that can also be programmed to be enhanced serial communication. PTE0/TXD is internally connected to the TXD terminal of the analog die. The connection for the receiver must be done externally.
Port B I/O Terminals
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. All terminals are shared with the ADC module. The PTB6:PTB7 terminals are also shared with the Timer B module. PTB0/AD0 is internally connected to the ADOUT terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2 terminal is not accessible in this device. For details refer to the 68HC908EY16 datasheet.
External Interrupt Terminal (IRQ)
The IRQ terminal is an asynchronous external interrupt terminal. This terminal contains an internal pullup resistor that is always activated, even when the IRQ terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet.
Port C I/O Terminals
These terminals are special-function, bidirectional I/O port terminals that are shared with other functional modules in the MCU. For example, PTC2:PTC4 are shared with the ICG module. PTC0/MISO and PTC1/MOSI are not accessible in this device and are internally connected to the MISO and MOSI SPI terminals of the analog die. For details refer to the 68HC908EY16 datasheet.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
External Reset Terminal (RST)
A logic [0] on the RST terminal forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven LOW when any internal reset source is asserted. This terminal contains an internal pullup resistor that is always activated, even when the reset terminal is pulled LOW. For details refer to the 68HC908EY16 datasheet.
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Current Limitation Frequency Input Terminal (FGEN)
Input terminal for the half-bridge current limitation and the high-side inrush current limiter PWM frequency. This input is not a real PWM input terminal; it should just supply the period of the PWM. The duty cycle will be generate automatically. Important The recommended FGEN frequency should be in the range of 0.1 kHz to 20 kHz. All VSUP terminals must be connected to get full chip functionality.
Power Ground Terminals (GND1 and GND2)
GND1 and GND2 are device power ground connections. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple terminals are provided. GND1 and GND2 terminals must be connected to get full chip functionality.
Back Electromagnetic Force Output Terminal (BEMF)
This terminal gives the user information about back electromagnetic force (BEMF). This feature is mainly used in step motor applications for detecting a stalled motor. In order to evaluate this signal the terminal must be directly connected to terminal PTD0/TACH0/BEMF.
High-Side Output Terminal (HS)
The HS output terminal is a low RDS(ON) high-side switch. The switch is protected against overtemperature and overcurrent. The output is capable of limiting the inrush current with an automatic PWM generation using the FGEN module.
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Reset Terminal (RST_A)
RST_A is the bidirectional reset terminal of the analog die. It is an open drain with pullup resistor and must be connected to the RST terminal of the MCU.
Switchable VDD Output Terminal (HVDD)
The HVDD terminal is a switchable VDD output for driving resistive loads requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors. The output is short-circuit protected.
Interrupt Terminal (IRQ_A)
IRQ_A is the interrupt output terminal of the analog die indicating errors or wake-up events. It is an open drain with pullup resistor and must be connected to the IRQ terminal of the MCU.
Hall-Effect Sensor Input Terminals (H1:H3)
The Hall-effect sensor input terminals H1:H3 provide inputs for Hall-effect sensors and switches.
Slave Select Terminal (SS)
This terminal is the SPI Slave Select terminal for the analog chip. All other SPI connections are done internally. SS must be connected to PTB1 or any other logic I/O of the microcontroller.
+5.0 V Voltage Regulator Output Terminal (VDD)
The VDD terminal is needed to place an external capacitor to stabilize the regulated output voltage. The VDD terminal is intended to supply the embedded microcontroller. Important The VDD terminal should not be used to supply other loads; use the HVDD terminal for this purpose. The VDD, EVDD, VDDA, and VREFH terminals must be connected together.
LIN Bus Terminal (LIN)
The LIN terminal represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification.
Half-Bridge Output Terminals (HB1:HB4)
The 908E625 device includes power MOSFETs configured as four half-bridge driver outputs. The HB1:HB4 outputs may be configured for step motor drivers, DC motor drivers, or as high-side and low-side switches. The HB1:HB4 outputs are short-circuit and overtemperature protected, and they feature current recopy, current limitation, and BEMF generation. Current limitation and recopy are done on the low-side MOSFETs.
Analog Input Terminal (PA1)
This terminal is an analog input port with selectable current source values.
Voltage Regulator Ground Terminal (VSS)
The VSS terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). Important VSS, EVSS, VSSA, and VREFL terminals must be connected together.
Power Supply Terminals (VSUP1:VSUP3)
VSUP1:VSUP3 are device power supply terminals. The nominal input voltage is designed for operation from 12 V systems. Owing to the low ON-resistance and current requirements of the half-bridge driver outputs and high-side output driver, multiple VSUP terminals are provided.
LIN Transceiver Output Terminal (RXD)
This terminal is the output of LIN transceiver. The terminal must be connected to the microcontroller's Enhanced Serial Communications Interface (ESCI) module (RXD terminal).
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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ADC Reference Terminals (VREFL and VREFH)
VREFL and VREFH are the reference voltage terminals for the ADC. It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VREFH is the high reference supply for the ADC and should be tied to the same potential as VDDA via separate traces. VREFL is the low reference supply for the ADC and should be tied to the same potential as VSS via separate traces. For details refer to the 68HC908EY16 datasheet.
MCU Power Supply Terminals (EVDD and EVSS)
EVDD and EVSS are the power supply and ground terminals. The MCU operates from a single power supply. Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU. For details refer to the 68HC908EY16 datasheet.
ADC Supply Terminals (VDDA and VSSA)
VDDA and VSSA are the power supply terminals for the analog-to-digital converter (ADC). It is recommended that a high-quality ceramic decoupling capacitor be placed between these terminals. Important VDDA is the supply for the ADC and should be tied to the same potential as EVDD via separate traces. VSSA is the ground terminal for the ADC and should be tied to the same potential as EVSS via separate traces. For details refer to the 68HC908EY16 datasheet.
Test Terminal (FLSVPP)
For test purposes only. Do not connect in the application.
Exposed Pad Terminal
The exposed pad terminal on the bottom side of the package conducts heat from the chip to the PCB board. For thermal performance the pad must be soldered to the PCB board. It is recommended that the pad be connected to the ground potential.
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ANALOG DIE DESCRIPTION Interrupts
The 908E625 has seven different interrupt sources as described in the following paragraphs. The interrupts can be disabled or enabled via the SPI. After reset all interrupts are automatically disabled. Low-Voltage Interrupt The Low-Voltage Interrupt (LVI) is related to the external supply voltage, VSUP. If this voltage falls below the LVI threshold, it will set the LVI flag. If the low-voltage interrupt is enabled, an interrupt will be initiated. With LVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the LVI circuitry is disabled. Hall-Effect Sensor Input Terminal Interrupt High-Voltage Interrupt The High-Voltage Interrupt (HVI) is related to the external supply voltage, VSUP. If this voltage rises above the HVI threshold, it will set the HVI flag. If the High-Voltage Interrupt is enabled, an interrupt will be initiated. With HVI the H-Bridges (high-side MOSFET only) and the high-side driver are switched off. All other modules are not influenced by this interrupt. During STOP mode the HVI circuitry is disabled. If the PHIE bit is set, the enabled Hall-effect sensor input terminals H1:H3 can generate an interrupt if a current above the threshold is detected. During STOP mode this interrupt, combined with the cyclic wake-up feature of the AWD, can wake up the system (refer to Hall-Effect Sensor Input Terminals (H1:H3) on page 25). Overcurrent Interrupt If an overcurrent condition on a half-bridge occurs, the highside or the HVDD output is detected and the OCIE bit is set and an interrupt generated. High-Temperature Interrupt The High-Temperature Interrupt (HTI) is generated by the on-chip temperature sensors. If the chip temperature is above the HTI threshold, the HTI flag will be set. If the HighTemperature Interrupt is enabled, an interrupt will be initiated. During STOP mode the HTI circuitry is disabled. Autonomous Watchdog Interrupt (AWD) Refer to Autonomous Watchdog (AWD) on page 36. LIN Interrupt If the LINIE bit is set, a falling edge on the LIN terminal will generate an interrupt. During STOP mode this interrupt will initiate a system wake-up.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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System Wake-Up
System wake-up can be initiated by any of four events: * A falling edge on the LIN terminal. * A wake-up signal from the AWD. * A logic [1] at Hall-effect sensor input terminal during cyclic check via AWD. * An LVR condition. If one of these wake-up events occurs and the interrupt mask bit for this event is set, the interrupt will wake up the microcontroller as well as the main voltage regulator (MREG) (Figure 6).
Bit7 Read Write Reset
0 0
Interrupt Flag Register (IFR)
Register Name and Address: IFR - $05 6
HPF 0
5
LINF 0
4
HTF 0
3
LVF 0
2
HVF 0
1
OCF
Bit0
0
0
0
HPF--Hall-Effect Sensor Input Terminal Flag Bit This read/write flag is set depending on RUN/STOP mode. RUN Mode An interrupt will be generated when a state change on any enabled Hall-effect sensor input terminal is detected. Clear HPF by writing a logic [1] to HPF. Reset clears the HPF bit. Writing a logic [0] to HPF has no effect. * 1 = State change on the hallflags detected. * 0 = No state change on the hallflags detected. STOP Mode An interrupt will be generated when AWDCC is set and a current above the threshold is detected on any enabled Hall-effect sensor input terminal. Clear HPF by writing a logic [1] to HPF. Reset clears the HPF bit. Writing a logic [0] to HPF has no effect. * 1 = One or more of the selected Hall-effect sensor input terminals had been pulled HIGH. * 0 = None of the selected Hall-effect sensor input terminals has been pulled HIGH.
MCU Die
Analog Die
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From Reset
Initialize
Operate
SPI: GS =1 (MREG off)
STOP MREG
LINF--LIN Flag Bit This read/write flag is set on the falling edge at the LIN data line. Clear LINF by writing a logic [1] to LINF. Reset clears the LINF bit. Writing a logic [0] to LINF has no effect. * 1 = Falling edge on LIN data line has occurred. * 0 = Falling edge on LIN data line has not occurred since last clear. HTF--High-Temperature Flag Bit This read/write flag is set on a high-temperature condition. Clear HTF by writing a logic [1] to HTF. If a high-temperature condition is still present while writing a logic [1] to HTF, the writing has no effect. Therefore, a high-temperature interrupt cannot be lost due to inadvertent clearing of HTF. Reset clears the HTF bit. Writing a logic [0] to HTF has no effect. * 1 = High-temperature condition has occurred. * 0 = High-temperature condition has not occurred.
STOP
Wait for Action LIN AWD Hallport
IRQ Interrupt?
Assert IRQ_A
SPI: Reason for Interrupt
Start MREG
Operate
MREG = Main Voltage Regulator
Figure 6. STOP Mode/Wake-Up Procedure
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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LVF--Low-Voltage Flag Bit This read/write flag is set on a low-voltage condition. Clear LVF by writing a logic [1] to LVF. If a low-voltage condition is still present while writing a logic [1] to LVF, the writing has no effect. Therefore, a low-voltage interrupt cannot be lost due to inadvertent clearing of LVF. Reset clears the LVF bit. Writing a logic [0] to LVF has no effect. * 1 = Low-voltage condition has occurred. * 0 = Low-voltage condition has not occurred. HVF--High-Voltage Flag Bit This read/write flag is set on a high-voltage condition. Clear HVF by writing a logic [1] to HVF. If high-voltage condition is still present while writing a logic [1] to HVF, the writing has no effect. Therefore, a high-voltage interrupt cannot be lost due to inadvertent clearing of HVF. Reset clears the HVF bit. Writing a logic [0] to HVF has no effect. * 1 = High-voltage condition has occurred. * 0 = High-voltage condition has not occurred. OCF--Overcurrent Flag Bit This read-only flag is set on an overcurrent condition. Reset clears the OCF bit. To clear this flag, write a logic [1] to the appropriate overcurrent flag in the SYSSTAT Register. See Figure 7, which shows the three signals triggering the OCF. * 1 = High-current condition has occurred. * 0 = High-current condition has not occurred. Interrupt Mask Register (IMR)
Register Name and Address: IMR - $04 Bit7 Read Write Reset
0 0
6
HPIE 0
5
LINIE 0
4
HTIE 0
3
LVIE 0
2
HVIE 0
1
OCIE 0
Bit0
0
0
HPIE--Hall-Effect Sensor Input Terminal Interrupt Enable Bit This read/write bit enables CPU interrupts by the Hall-effect sensor input terminal flag, HPF. Reset clears the HPIE bit. * 1 = Interrupt requests from HPF flag enabled. * 0 = Interrupt requests from HPF flag disabled. LINIE--LIN Line Interrupt Enable Bit This read/write bit enables CPU interrupts by the LIN flag, LINF. Reset clears the LINIE bit. * 1 = Interrupt requests from LINF flag enabled. * 0 = Interrupt requests from LINF flag disabled. HTIE--High-Temperature Interrupt Enable Bit This read/ write bit enables CPU interrupts by the hightemperature flag, HTF. Reset clears the HTIE bit. * 1 = Interrupt requests from HTF flag enabled. * 0 = Interrupt requests from HTF flag disabled. LVIE--Low-Voltage Interrupt Enable Bit This read/write bit enables CPU interrupts by the lowvoltage flag, LVF. Reset clears the LVIE bit. * 1 = Interrupt requests from LVF flag enabled. * 0 = Interrupt requests from LVF flag disabled. HVIE--High-Voltage Interrupt Enable Bit This read/write bit enables CPU interrupts by the highvoltage flag, HVF. Reset clears the HVIE bit. * 1 = Interrupt requests from HVF flag enabled. * 0 = Interrupt requests from HVF flag disabled. OCIE--Overcurrent Interrupt Enable Bit This read/write bit enables CPU interrupts by the overcurrent flag, OCF. Reset clears the OCIE bit. * 1 = Interrupt requests from OCF flag enabled. * 0 = Interrupt requests from OCF flag disabled.
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HVDD_OCF HS_OCF HB_OCF
OCF
Figure 7. Principal Implementation for OCF
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Reset
The 908E625 chip has four internal reset sources and one external reset source, as explained in the paragraphs below. Figure 8 depicts the internal reset sources.
SPI REGISTERS
AWDRE Flag AWD Reset Sensor HVRE Flag High-Voltage Reset Sensor
VDD
HTRE Flag
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RST_A
High-Temperature Reset Sensor
MONO FLOP Low-Voltage Reset
Figure 8. Internal Reset Routing
Reset Internal Sources
Autonomous Watchdog AWD modules generates a reset because of a timeout (watchdog function). High-Temperature Reset To prevent damage to the device, a reset will be initiated if the temperature rises above a certain value. The reset is maskable with bit HTRE in the Reset Mask Register. After a reset the high-temperature reset is disabled. Low-Voltage Reset The LVR is related to the internal VDD. In case the voltage falls below a certain threshold, it will pull down the RST_A terminal. High-Voltage Reset The HVR is related to the external VSUP voltage. In case the voltage is above a certain threshold, it will pull down the RST_A terminal. The reset is maskable with bit HVRE in the Reset Mask Register. After a reset the high-voltage reset is disabled.
Reset External Source
External Reset Terminal The microcontroller has the capability of resetting the SMARTMOS device by pulling down the RST terminal. Reset Mask Register (RMR)
Register Name and Address: RMR - $06 Bit7 Read Write Reset
TTEST 0
6
0
5
0
4
0
3
0
2
0
1
HVRE 0
Bit0
HTRE 0
0
0
0
0
0
TTEST--High-Temperature Reset Test This read/write bit is for test purposes only. It decreases the overtemperature shutdown limit for final test. Reset clears the HTRE bit. * 1 = Low-temperature threshold enabled. * 0 = Low-temperature threshold disabled.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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HVRE--High-Voltage Reset Enable Bit This read/write bit enables resets on high-voltage conditions. Reset clears the HVRE bit. 1 = High-voltage reset enabled. 0 = High-voltage reset disabled. HTRE--High-Temperature Reset Enable Bit This read/write bit enables resets on high-temperature conditions. Reset clears the HTRE bit. * 1 = High-temperature reset enabled. * 0 = High-temperature reset disabled.
SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) creates the communication link between the microcontroller and the 908E625. The interface consists of four terminals (see Figure 9): A complete data transfer via the SPI consists of 2 bytes. The master sends address and data, slave system status, and data of the selected address.
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* * * *
SS--Slave Select MOSI--Master-Out Slave-In MISO--Master-In Slave-Out SPSCK--Serial Clock
SS
Read/Write, Address, Parity
Data (Register write) P X D7 D6 D5 D4 D3 D2 D1 D0
MOSI
R/W
A4
A3
A2
A1
A0
System Status Register
Data (Register read) S1 S0 D7 D6 D5 D4 D3 D2 D1 D0
MISO
S7
S6
S5
S4
S3
S2
SPSCK
Rising edge of SPSCK Change MISO/MOSI Output Falling edge of SPSCK Sample MISO/MOSI Input Slave latch register address Slave latch data
Figure 9. SPI Protocol During the inactive phase of SS, the new data transfer is prepared. The falling edge on the SS line indicates the start of a new data transfer and puts MISO in the low-impedance mode. The first valid data are moved to MISO with the rising edge of SPSCK. The MISO output changes data on a rising edge of SPSCK. The MOSI input is sampled on a falling edge of SPSCK. The data transfer is only valid if exactly 16 sample clock edges are present in the active phase of SS. After a write operation, the transmitted data is latched into the register by the rising edge of SS. Register read data is internally latched into the SPI at the time when the parity bit is transferred. SS HIGH forces MISO to high impedance.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Master Address Byte
A4:A0 Contains the address of the desired register. R/W Contains information about a read or a write operation. * If R/W = 1, the second byte of master contains no valid information, slave just transmits back register data. * If R/W = 0, the master sends data to be written in the second byte, slave sends concurrently contents of selected register prior to write operation, write data is latched in the SMARTMOS register on rising edge of SS. Bit X Not used. Master Data Byte Contains data to be written or no valid data during a read operation. Slave Status Byte Contains the contents of the System Status Register ($0c) independent of whether it is a write or read operation or which register was selected. Slave Data Byte Contains the contents of selected register. During a write operation it includes the register content prior to a write operation.
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Parity P The parity bit is equal to "0" if the number of 1 bits is an even number contained within R/W, A4:A0. If the number of 1 bits is odd, P equals "1". For example, if R/W = 1, A4:A0 = 00001, then P equals "0." The parity bit is only evaluated during a write operation.
SPI Register Overview
Table 1 summarizes the SPI Register addresses and the bit names of each register.
Table 1. List of Registers
Addr Register Name H-Bridge Output (HBOUT) H-Bridge Control (HBCTL) System Control (SYSCTL) Interrupt Mask (IMR) Interrupt Flag (IFR) Reset Mask (RMR) Analog Multiplexer Configuration (ADMUX) Hall-Effect Sensor Input Terminal Control (HACTL) Hall-Effect Sensor Input Terminal Status (HASTAT) AWD Control (AWDCTL) Power Output (POUT) System Status (SYSSTAT) R/W R W R W R W R W R W R W R W R W R W R W R W R W HP_OCF LINCL 0 0 0 0 0 AWDRST CSSEL1 AWDRE AWDIE AWDCC AWDF AWDR 0 0 0 0 0 H3F H2F H1F 0 0 0 0 Bit 7 HB4_H 6 HB4_L 5 HB3_H 0 4 HB3_L 0 3 HB2_H 0 2 HB2_L 1 HB1_H 0 HB1_L
$01
$02
OFC_EN
CSA
CLS2 0
CLS1 0
CLS0 0 GS
$03
PSON
SRS1
SRS0
0
0
$04
0
HPIE
LINIE
HTIE
LVIE
HVIE
OCIE OCF
0
$05
0
HPF 0
LINF 0
HTF 0
LVF 0
HVF 0
0
$06
TTEST 0
HVRE
HTRE
$07
0
0
0
SS3 0
SS2
SS1
SS0
$08
H3EN
H2EN
H1EN
$09
$0a
$0b
CSSEL0
CSEN1 LVF
CSEN0 HVF
HVDDON
HS_ON HTF
$0c
HVDD_OCF HS_OCF
HB_OCF
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Analog Die I/Os
LIN Physical Layer The LIN bus terminal provides a physical layer for single-wire communication in automotive applications. The LIN physical layer is designed to meet the LIN physical layer specification. The LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. The fall time from dominant to recessive and the rise time from recessive to dominant is controlled. The symmetry between both slew rate controls is guaranteed. Analog Multiplexer/ADOUT Terminal The ADOUT terminal is the analog output interface to the ADC of the MCU (see Figure 1, page 2). An analog multiplexer is used to read seven internal diagnostic analog voltages. Current Recopy The analog multiplexer is connected to the four low-side current sense circuits of the half-bridges. These sense circuits offer a voltage proportional to the current through the low-side MOSFET. High or low resolution is selectable: 5.0 V/2.5 A or 5.0 V/500 mA, respectively. (Refer to Half-Bridge Current Recopy on page 31.) Analog Input PA1 The analog input PA1 is directly connected to the analog multiplexer, permitting analog values from the periphery to be read. Temperature Sensor The 908E625 includes an on-chip temperature sensor. This sensor offers a voltage that is proportional to the actual chip junction temperature. VSUP Prescaler The VSUP prescaler permits the reading or measurement of the external supply voltage. The output of this voltage is VSUP / RATIOVSUP. The different internal diagnostic analog voltages can be selected with the ADMUX Register. Analog Multiplexer Configuration Register (ADMUX)
Register Name and Address: ADMUX - $07 Bit7 Read Write
0
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The LIN terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. The LIN transmitter circuitry is enabled by setting the PSON bit in the System Control Register (SYSCTL). If the transmitter works in the current limitation region, the LINCL bit in the System Status Register (SYSSTAT) is set. Due to excessive power dissipation in the transmitter, software is advised to monitor this bit and turn the transmitter off immediately. TXD Terminal The TXD terminal is the MCU interface to control the state of the LIN transmitter (see Figure 1, page 2). When TXD is LOW, LIN output is low (dominant state). When TXD is HIGH, the LIN output MOSFET is turned off. The TXD terminal has an internal pullup current source in order to set the LIN bus in recessive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. RXD Terminal The RXD transceiver terminal is the MCU interface, which reports the state of the LIN bus voltage. LIN HIGH (recessive state) is reported by a high level on RXD, LIN LOW (dominant state) by a low level on RXD. STOP Mode/Wake-Up Feature During STOP mode operation the transmitter of the physical layer is disabled. The receiver terminal is still active and able to detect wake-up events on the LIN bus line. If LIN interrupt is enabled (LINIE bit in the Interrupt Mask Register is set), a falling edge on the LIN line causes an interrupt. This interrupt switches on the main voltage regulator and generates a system wake-up.
6
0
5
0
4
0
3
SS3
2
SS2 0
1
SS1 0
Bit0
SS0 0
Reset
0
0
0
0
0
SS3, SS2, SS1, and SS0--A/D Input Select Bits These read/write bits select the input to the ADC in the microcontroller according to Table 2, page 24. Reset clears SS3, SS2, SS1, and SS0 bits.
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Table 2. Analog Multiplexer Configuration Register
SS3 0 0 0 0 0 0 0 0 1 SS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Not Used Channel Current Recopy HB1 Current Recopy HB2 Current Recopy HB3 Current Recopy HB4 VSUP Prescaler Temperature Sensor Not Used PA1 Terminal
Analog Input PA1 The Analog input PA1 terminal provides an input for reading analog signals and is internally connected to the analog multiplexer. It can be used for reading switches, potentiometers or resistor values, etc. Analog Input PA1 Current Source The analog input PA1 has an additional selectable current source. It enables the reading of switches, NTC, etc., without the need of an additional supply line for the sensor (Figure 10). With this feature it is also possible to read multiple switches on one input. Current source is enabled if the PSON bit in the System Control Register (SYSCTL) and the CSEN bit in the Power Output Register (POUT) is set. Four different current source values can be selected with the CSSELx bits (Table 3). This function ceases during STOP mode operation. Table 3. PA1 Current Source Level Selection Bits
CSSEL1 0 0 1 1 CSSEL0 0 1 0 1 Current Source Enable (typ.) 10% 30% 60% 100%
Freescale Semiconductor, Inc...
1 1 1 1 1 1 1
Source Selection Bits SSx 3 Selectable Current Source
VDD
CSSEL
PSON
ADOUT
Analog Multiplexer
CSEN
PA1
Analog Input PA1 NTC
Figure 10. Analog Input PA1 and Multiplexer6
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
Power Output Register (POUT)
Register Name and Address: POUT - $0b Bit7 Read Write Reset
0 0 0
Hall-Effect Sensor Input Terminals (H1:H3)
Function
1
HVDDON
6
0
5
CSSEL1
4
CSSEL0
3
CSEN
2
0
(Note 17)
Bit0
HS_ON
0
0
0
0
0
0
The Hall-effect sensor input terminals provide three inputs for two-terminal Hall-effect sensors for detecting stall and position or reading Hall-effect sensor contact switches. The Hall-effect sensor input terminals are not influenced by the PSON bit in the System Control Register. Each terminal of the Hall-effect sensor can be enabled by setting the HxEN bit in the Hall-Effect Sensor Input Terminal Control Register (HACTL). If the terminals are enabled, the Hall-effect sensors are supplied with VSUP voltage and the sense circuitry is working. An internal clamp circuity limits the supply voltage to the sensor to 15 V. This sense circuitry monitors the current to VSS. The result of this sense operation is given by the HxF flags in the Hall-Effect Sensor Input Terminal Status Register (HASTAT). The flag is set if the sensed current is higher than IHSCT. To prevent noise on this flag, a hysteresis is implemented on these terminals. After switching on the Hall-effect sensor input terminals (HxEN = 1), the Hall-effect sensors need some time to stabilize the output. In RUN mode the software must wait at least 40 s between enabling the Hall-effect sensor and reading the hallflag. The Hall-effect sensor input terminal works in an dynamic output voltage range from VSUP down to 2.0 V. Below 2.0 V the hallflags are not functional anymore. If the output voltage is below a certain threshold, the Hall-Effect Sensor Input Terminal Overcurrent Flag (HP_OCF) in the System Status Register is set. Figures 11 through 13, pp. 26-27, show the connections to the Hall-effect input sensors.
Notes 17. This bit must always be set to 0.
CSSEL0:CSSEL1--Current Source Select Bits This read/write bit selects the current source values. Reset clears the CSSEL0:CSSEL1 bits. CSEN--Current Source Enable Bit This read/write bit enables the current source for PA1. Reset clears the CSEN bit (Table 4). Table 4. PA1 Current Source Enable Bit
CSEN 0 1 Current Source Enable Current Source Off Current Source On
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HVDDON--HVDD On Bit This read/write bit enables HVDD output. Reset clears the HVDDON bit. * 1 = HVDD enabled. * 0 = HVDD disabled. HS_ON--Lamp Driver On Bit This read/write bit enables the Lamp driver. Reset clears the HS_ON bit. * 1 = Lamp driver enabled. * 0 = Lamp driver disabled.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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908E625 25
Freescale Semiconductor, Inc.
HxEN Sense Circuitry Hx
Two-Terminal Hall-Effect Sensor
HxF
Freescale Semiconductor, Inc...
V
GND
Figure 11. Hall-Effect Sensor Input Terminal Connected to Two-Terminal Hall-Effect Sensor
HxEN Sense Circuitry Hx Rv
HxF
V
GND
Figure 12. Hall-Effect Sensor Input Terminal Connected to Local Switch
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
Three-Terminal Hall-Effect Sensor Vs HxEN Sense Circuitry Hx Out
HxF
Freescale Semiconductor, Inc...
V
GND
GND
Figure 13. Hall-Effect Sensor Input Terminal Connected to Three-Terminal Hall-Effect Sensor Interrupts The Hall-effect sensor input terminals are interrupt capable. How and when an interrupt occurs is dependent on the operating mode, RUN or Stop. RUN Mode In RUN mode the Hall-effect sensor input terminal interrupt flag (HPF) will be set if a state change on the hallflags (HxF) is detected. The interrupt is maskable with the HPIE bit in the Interrupt Mask Register. Before enabling the interrupt, the flag should be cleared in order to prevent a wrong interrupt. STOP Mode In STOP mode the Hall-effect sensor input terminals are disabled independent of the state of the HxEN flags. Cyclic Wake-Up The Hall-effect sensor inputs can be used to wake up the system. This wake-up function is provided by the cyclic check wake-up feature of the AWD (autonomous watchdog). If the cyclic check wake-up feature is enabled (AWDCC bit is set), the AWD switches on the enabled Hall-effect sensor terminals periodically. To ensure that the Hall-effect sensor current is stabilized after switching on, the inputs are sensed after ~40 s. If a "1" is detected (IHall sensor > IHSCT) and the interrupt mask bit HPIE is set, an interrupt is performed. This wakes up the MCU and starts the main voltage regulator. The wake-up function via this input is available when all three conditions exist: * The two-terminal Hall-effect sensor input is enabled (HxEN = 1). * The cyclic wake-up of the AWD is enabled (AWDCC = 1) (see Figure 14, page 28). * The Hall-effect sensor input terminal interrupt is enabled (HPIE = 1).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
SPI: AWDCC = 1 GS = 1
SPI Command
STOP MREG
STOP
No
AWD Timer Overflow? Yes
No
IRQ? IRQ_A = 0 Start MREG
Switch on Selected Hallport
Freescale Semiconductor, Inc...
Yes SPI: Reason for Wakeup
Wait 40 s
Operate
Assert IRQ_A
Yes
Hallport = 1
No
Switch off Selected Hallport MREG = Main Voltage Regulator
Figure 14. Hall-Effect Sensor Input Terminal Cyclic Check Wake-Up Feature Hall-Effect Sensor Input Terminal Control Register (HACTL)
Register Name and Address: HACTL - $08 Bit7 Read Write Reset
0 0 0 0 0 0
Hall-Effect Sensor Input Terminal Status Register (HASTAT)
Register Name and Address: HASTAT - $09
6
0
5
0
4
0
3
0
2
H3EN 0
1
H2EN 0
Bit0
H1EN 0
Bit7 Read Write Reset
0 0
6
0
5
0
4
0
3
0
2
H3F
1
H2F
Bit0
H1F
0
0
0
0
0
0
0
H3EN:H1EN--Hall-Effect Sensor Input Terminal Enable Bits These read/write bits enable the Hall-effect sensor input terminals. Reset clears the H3EN:H1EN bits. * 1 = Hall-effect sensor input terminal Hx switched on and sensed. * 0 = Hall-effect sensor input terminal Hx disabled.
H3F:H1F--Hall-Effect Sensor Input Terminal Flag Bits These read-only flag bits reflect the input Hx while the Halleffect sensor input terminal Hx is enabled (HxEN = 1). Reset clears the H3F:H1F bits. * 1 = Hall-effect sensor input terminal current above threshold. * 0 = Hall-effect sensor input terminal current below threshold.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
Half-Bridges
Outputs HB1:HB4 provide four low-resistive half-bridge output stages. The half-bridges can be used in H-Bridge, highside, or low-side configurations. Reset clears all bits in the H-Bridge Output Register (HBOUT) owing to the fact that all half-bridge outputs are switched off. HB1:HB4 output features: * Short circuit (overcurrent) protection on high-side and lowside MOSFETs. * Current recopy feature (low side MOSFET). * Overtemperature protection. * Overvoltage and undervoltage protection. * Current limitation feature (low side MOSFET).
VSUP
On/Off
High-Side Driver
Charge Pump, Overtemperature Protection, Overcurrent Protection
Freescale Semiconductor, Inc...
Status
Control
BEMF
HBx
On/Off Status Current Limit
Low-Side Driver
Current Recopy, Current Limitation, Overcurrent Protection
GND
Figure 15. Half-Bridge Push-Pull Output Driver Half-Bridge Control Each output MOSFET can be controlled individually. The general enable of the circuitry is done by setting PSON in the System Control Register (SYSCTL). HBx_L and HBx_H form one half-bridge. It is not possible to switch on both MOSFETs in one half-bridge at the same time. If both bits are set, the highside MOSFET has a higher priority. To avoid both MOSFETs (high side and low side) of one halfbridge being on at the same time, a break-before-make circuit exists. Switching the high-side MOSFET on is inhibited as long as the potential between gate and VSS is not below a certain threshold. Switching the low-side MOSFET on is blocked as long as the potential between gate and source of the high-side MOSFET did not fall below a certain threshold. Half-Bridge Output Register (HBOUT)
Register Name and Address: HBOUT - $01 Bit7 Read Write Reset 6 5 4 3 2 1 Bit0
HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L 0 0 0 0 0 0 0 0
HBx_L--Low-Side On/Off Bits These read/write bits turn on the low-side MOSFETs. Reset clears the HBx_L bits. * 1 = Low-side MOSFET turned on for half-bridge output x. * 0 = Low-side MOSFET turned off for half-bridge output x.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
HBx_H--High-Side On/Off Bits These read/write bits turn on the high-side MOSFETs. Reset clears the HBx_H bits. 1 = High-side MOSFET turned on for half-bridge output x. 0 = High-side MOSFET turned on for half-bridge output x. the load characteristics. The FGEN input provides the PWM frequency, whereas the duty cycle is controlled by the load characteristics. The recommended frequency range for the FGEN and the PWM is 0.1 kHz to 20 kHz. Functionality Each low-side MOSFET switches off if a current above the selected current limit was detected. The 908E625 offers five different current limits (refer to Table 5, page 33, for current limit values). The low-side MOSFET switches on again if a rising edge on the FGEN input was detected (Figure 16).
H-Bridge low-side MOSFET will be switched off if select current limit is reached.
Half-Bridge Current Limitation
Each low-side MOSFET offers a current limit or constant current feature. This features is realized by a pulse width modulation on the low-side MOSFET. The pulse width modulation on the outputs is controlled by the FGEN input and
Freescale Semiconductor, Inc...
Coil Current
H-Bridge low-side MOSFET will be turned on with each rising edge of the FGEN input. t (s) Half-Bridge Low-Side Output
t (s) FGEN Input (MCU PWM Signal)
t (s) Minimum 50 s
Figure 16. Half-Bridge Current Limitation
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
Offset Chopping If bit OFC_EN in the H-Bridge Control Register (HBCTL) is set, HB1 and HB2 will continue to switch on the low-side MOSFETs with the rising edge of the FGEN signal and HB3 and
Coil1 Current
HB4 will switch on the low-side MOSFETs with the falling edge on the FGEN input. In step motor applications this feature allows the reduction of EMI due to a reduction of the di/dt (Figure 17).
Freescale Semiconductor, Inc...
Coil2 Current
FGEN Input (MCU PWM Signal)
HB1 HB2 HB3 HB4
Coil1.....
Coil2.....
Current in VSUP Line
Figure 17. Offset Chopping for Step Motor Control
Half-Bridge Current Recopy
Each low-side MOSFET has an additional sense output to allow a current recopy feature. This sense source is internally connected to a shunt resistor. The drop voltage is amplified and switched to the analog multiplexer. The factor for the current sense amplification can be selected via bit CSA in the System Control Register. * CSA = 1: Low resolution selected (500 mA measurement range). * CSA = 0: High resolution selected (2.5 A measurement range).
Half-Bridge BEMF Generation
The BEMF output is set to "1" if a recirculation current is detected in any half-bridge. This recirculation current flows via the two freewheeling diodes of the power MOSFETs. The BEMF circuitry detects that and generates a HIGH on the BEMF output as long as a recirculation current is detected. This signal provides a flexible and reliable detection of stall in step motor applications. For this the BEMF circuitry takes advantage of the instability of the electrical and mechanical behavior of a step motor when blocked. In addition the signal can be used for open load detection (absence of this signal) (see Figure 18, page 32).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
Coil Current
Voltage on 1
1
Freescale Semiconductor, Inc...
BEMF Signal
Figure 18. BEMF Signal Generation
Half-Bridge Overtemperature Protection
The half-bridge outputs provide an overtemperature prewarning with the HTF in the Interrupt Flag Register (IFR). In order to protect the outputs against overtemperature, the HighTemperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs.
The overvoltage/undervoltage status flags are cleared (and the outputs re-enabled) by writing a logic [1] to the LVF/HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present. Half-Bridge Control Register (HBCTL)
Register Name and Address: HBCTL - $02 Bit7 Read Write Reset
OFC_EN 0
Half-Bridge Overcurrent Protection
The half-bridges are protected against short to GND, short to VSUP, and load shorts. In the event an overcurrent on the high side is detected, the high-side MOSFETs on all HB high-side MOSFETs are switched off automatically. In the event an overcurrent on the low side is detected, all HB low-side MOSFETs are switched off automatically. In both cases the overcurrent status flag HB_OCF in the System Status Register (SYSSTAT) is set. The overcurrent status flag is cleared (and the outputs reenabled) by writing a logic [1] to the HB_OCF flag in the System Status Register or by reset.
6
CSA 0
5
0
4
0
3
0
2
CLS2
1
CLS1 0
Bit0
CLS0 0
0
0
0
0
OFC_EN--H-Bridge Offset Chopping Enable Bit This read/write bit enables offset chopping. Reset clears the OFC_EN bit. * 1 = Offset chopping enabled. * 0 = Offset chopping disabled. CSA--H-Bridges Current Sense Amplification Select Bit This read/write bit selects the current sense amplification of the H-Bridges. Reset clears the CSA bit. * 1 = Current sense amplification set for measuring 0.5 A. * 0 = Current sense amplification set for measuring 2.5 A.
Half-Bridge Overvoltage/Undervoltage
The half-bridge outputs are protected against undervoltage and overvoltage conditions. This protection is done by the lowand high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the outputs are automatically disabled.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
CLS2:CLS0--H-Bridge Current Limitation Selection Bits These read/write bits select the current limitation value according to Table 5. Reset clears the CLS2:CLS0 bits. Table 5. H-Bridge Current Limitation Value Selection Bits
CLS2 0 0 0 0 1 1 CLS1 0 0 1 1 0 0 1 1 CLS0 0 1 0 1 0 1 0 1 55 mA (typ) 260 mA (typ) 370 mA (typ) 550 mA (typ) 740 mA (typ) No Limit Current Limit
High-Side Driver
The high-side output is a low-resistive high-side switch targeted for driving lamps. The high side is protected against overtemperature. To limit the high inrush current of bulbs, overcurrent protection circuitry is used to limit the current. The output is enabled with bit PSON in the System Control Register and can be switched on/off with bit HS_ON in the Power Output Register. Figure 19 depicts the high-side switch circuitry and connection to external lamp.
High-Side Overvoltage/Undervoltage Protection
The high-side output terminal, HS, is protected against undervoltage/overvoltage conditions. This protection is done by the low- and high-voltage interrupt circuitry. If one of these flags (LVF, HVF) is set, the output is disabled. The overvoltage/undervoltage status flags are cleared and the output re-enabled by writing a logic [1] to the LVF/HVF flags in the Interrupt Flag Register or by reset. Clearing this flag is useless as long as a high- or low-voltage condition is present.
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1 1
VSUP
On/Off Status Current Limit
High-Side Driver
Charge Pump, Overcurrent Protection, Inrush Current Limiter HS
Control
Figure 19. High-Side Circuitry
High-Side Overtemperature Protection
The high-side output provides an overtemperature prewarning with the HTF in the Interrupt Flag Register. In order to protect the output against overtemperature, the HighTemperature Reset must be enabled. If this value is reached, the part generates a reset and disables all power outputs.
High-Side Overcurrent Protection
The high-side output is protected against overcurrent. In the event overcurrent limit is or was reached, the output automatically switches off and the overcurrent flag is set.
Due to the high inrush current of bulbs, a special feature of the 908E625 prevents an overcurrent shutdown during this inrush. If an PWM frequency is supplied to the FGEN output during the switching on of a bulb, the inrush current is limited to the overcurrent shutdown limit. This means if the current reaches the overcurrent shutdown, the high side will be switched off, but each rising edge on the FGEN input will enable the driver again. To distinguish between a shutdown due to an inrush current or a real shutdown, the software must check if the overcurrent status flag (HS_OCF) in the System Status Register is set beyond a certain period of time. The overcurrent status flag is cleared by writing a logic [1] to the HS_OCF in the System Status Register (see Figure 20, page 34).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
HS Current
HS Overcurrent Shutdown Threshold
t
Freescale Semiconductor, Inc...
FGEN Input (MCU PWM Signal)
t
Figure 20. Inrush Current Limiter on High-Side Output
Switchable VDD Outputs
The HVDD terminal is a switchable VDD output terminal. It can be used for driving external circuitry that requires a VDD voltage. The output is enabled with bit PSON in the System Control Register and can be switched on/off with bit HVDDON in the Power Output Register. Low- or high-voltage conditions (LVI/HVI) have no influence on this circuitry.
System Control Register (SYSCTL)
Register Name and Address: SYSCTL - $03 Bit7 Read Write Reset
PSON 0
6
SRS1 0
5
SRS0 0
4
0
3
0
2
0
1
0
Bit0
0 GS
0
0
0
0
0
HVDD Overtemperature Protection
Overtemperature protection is enabled if the hightemperature reset is enabled. PSON--Power Stages On Bit This read/write bit enables the power stages (half-bridges, high side, LIN transmitter, Analog Input PA1 current sources, and HVDD output). Reset clears the PSON bit. * 1 = Power stages enabled. * 0 = Power stages disabled.
HVDD Overcurrent Protection
The HVDD output is protected against overcurrent. In the event the overcurrent limit is or was reached, the output automatically switches off and the HVDD overcurrent flag in the System Status Register is set.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
SRS0:SRS1--LIN Slew Rate Selection Bits These read/write bits enable the user to select the appropriate LIN slew rate for different baud rate configurations as shown in Table 6. The high speed slew rates are used, for example, for programming via the LIN and are not intended for use in the application. Table 6. LIN Slew Rate Selection Bits
SRS1 0 0 1 SRS0 0 1 0 1 LIN Slew Rate Initial Slew Rate (20 kBaud) Slow Slew Rate (10 kBaud) High Speed II (8x) High Speed I (4x)
HVDD_OCF--HVDD Output Overcurrent Flag Bit This read/write flag is set on an overcurrent condition at the HVDD terminal. Clear HVDD_OCF and enable the output by writing a logic [1] to the HVDD_OCF Flag. Reset clears the HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect. * 1 = Overcurrent condition on HVDD has occurred. * 0 = No overcurrent condition on HVDD has occurred. HS_OCF--High-Side Overcurrent Flag Bit This read/write flag is set on an overcurrent condition at the high-side driver. Clear HS_OCF and enable the high-side driver by writing a logic [1] to HS_OCF. Reset clears the HS_OCF bit. Writing a logic [0] to HS_OCF has no effect. * 1 = Overcurrent condition on high-side drivers has occurred. * 0 = No overcurrent condition on high-side drivers has occurred. LVF--Low-Voltage Bit This read only bit is a copy of the LVF bit in the Interrupt Flag Register. * 1 = Low-voltage condition has occurred. * 0 = No low-voltage condition has occurred. HVF--High-Voltage Sensor Bit
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1
GS--Go to STOP Mode Bit This write-only bit instructs the 908E625 to power down and go into STOP mode. Reset or CPU interrupt requests clear the GS bit. * 1 = Power down and go into STOP mode. * 0 = Not in STOP mode. System Control Register (SYSSTAT)
Register Name and Address: SYSSTAT - $0c Bit7 Read Write Reset
HP_ OCF 0
6
LINCL
5
HVDD _OCF 0
4
HS_ OCF 0
3
LVF
2
HVF
1
HB_ OCF 0
Bit0
HTF
This read-only bit is a copy of the HVF bit in the Interrupt Flag Register. * 1 = High-voltage condition has occurred. * 0 = No high-voltage condition has occurred.
0
0
0
0
HB_OCF--H-Bridge Overcurrent Flag Bit This read / write flag is set on an overcurrent condition at the H-Bridges. Clear HB_OCF and enable the H-Bridge driver by writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit. Writing a logic [0] to HB_OCF has no effect. * 1 = Overcurrent condition on H-Bridges has occurred. * 0 = No overcurrent condition on H-Bridges has occurred. HTF--Overtemperature Status Bit This read-only bit is a copy of the HTF bit in the Interrupt Flag Register. * 1 = Overtemperature condition has occurred. * 0 = No overtemperature condition has occurred.
HP_OCF--Hall-Effect Sensor Input Terminal Overcurrent Flag Bit This read/write flag is set on an overcurrent condition at one of the Hall-effect sensor input terminals. Clear HP_OCF and enable the output by writing a logic [1] to the HP_OCF flag. Reset clears the HP_OCF bit. Writing a logic [0] to HP_OCF has no effect. * 1 = Overcurrent condition on Hall-effect sensor input terminal has occurred. * 0 = No overcurrent condition on Hall-effect sensor input terminal has occurred. LINCL -- LIN Current Limitation Bit This read-only bit is set if the LIN transmitter operates in current limitation region. Due to excessive power dissipation in the transmitter, software is advised to turn the transmitter off immediately. * 1 = Transmitter operating in current limitation region. * 0 = Transmitter not operating in current limitation region.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Autonomous Watchdog (AWD)
The Autonomous Watchdog module consists of three functions: * Watchdog function for the CPU in RUN mode * Periodic interrupt function in STOP mode * Cyclic wake-up function in STOP mode The AWD is enabled if AWDIE, AWDRE, or AWDCC in the AWDCTL Register is set. If these bits are cleared, the AWD oscillator is disabled and the watchdog switched off. Watchdog The watchdog function is only available in RUN mode. On setting the AWDRE bit, watchdog functionality in RUN mode is activated. Once this function is enabled, it is not possible to disable it via software. If the timer reaches end value and AWDRE is set, a system reset is initiated. Operations of the watchdog function cease in STOP mode. Normal operation will be continued when the system is back to RUN mode. To prevent a watchdog reset, the watchdog timeout counter must be reset before it reaches the end value. This is done by a write to the AWDRST bit in the AWDCTL Register. Periodic Interrupt Periodic interrupt is only available in STOP mode. It is enabled by setting the AWDIE bit in the AWDCTL Register. If AWDIE is set, the AWD wakes up the system after a fixed period of time. This time period can be selected with bit AWDR in the AWDCTL Register. Cyclic Wake-Up The cyclic wake-up feature is only available in STOP mode. If this feature is enabled, the selected Hall-effect sensor input terminals are switched on and sensed. If a "1" is detected on one of these inputs and the interrupt for the Hall-effect sensors is enabled, a system wake-up is performed. (Switch on main voltage regulator and assert IRQ_A to the microcontroller). Autonomous Watchdog Control Register (AWDCTL)
Register Name and Address: AWDCTL - $0a Bit7 Read Write Reset
0 0 0
AWDRE--Autonomous Watchdog Reset Enable Bit This read/write bit enables resets on AWD timeouts. A reset on the RST_A is only asserted when the device is in RUN mode. AWDRE is one-time setable (write once) after each reset. Reset clears the AWDRE bit. * 1 = Autonomous watchdog enabled. * 0 = Autonomous watchdog disabled. AWDIE--Autonomous Watchdog Interrupt Enable Bit This read/write bit enables CPU interrupts by the Autonomous Watchdog timeout flag, AWFD. IRQ_A is only asserted when the device is in STOP mode. Reset clears the AWDIE bit. * 1 = CPU interrupt requests from AWDF enabled. * 0 = CPU interrupt requests from AWDF disabled. AWDCC-- Autonomous Watchdog Cyclic Check This read/write bit enables the cyclic check of the twoterminal Hall-effect sensor and the analog inputs. Reset clears the AWDCC bit. * 1 = Cyclic check of the Hall-effect sensor and analog port. * 0 = No cyclic check of the Hall-effect sensor and analog port. AWDF--Autonomous Watchdog Timeout Flag Bit This read/write flag is set when the Autonomous Watchdog has timed out. Clear AWDF by writing a logic [1] to AWDF. Clearing AWDF also resets the AWD counter and starts a new timeout period. Reset clears the AWDF bit. Writing a logic [0] to AWDF has no effect. * 1 = AWD has timed out. * 0 = AWD has not yet timed out. AWDR--Autonomous Watchdog Rate Bit This read/write bit selects the clock rate of the Autonomous Watchdog. Reset clears the AWDR bit. * 1 = Fast rate selected (10 ms). * 0 = Slow rate selected (20 ms).
Freescale Semiconductor, Inc...
Voltage Regulator
1 Bit0
AWDR
6
0
5
0
AWDRST
4
ADRE
3
AWDIE
2
AWDCC
AWDF
The 908E625 chip contains a low-power, low-drop voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts a unregulated input supply and provides a regulated VDD supply to all digital sections of the device. The output of the regulator is also connected to the VDD terminal to provide the 5.0 V to the microcontroller.
0
0
0
0
0
0
AWDRST--Autonomous Watchdog Reset Bit This write-only bit resets the Autonomous Watchdog timeout period. AWDRST always reads 0. Reset clears AWDRST bit. * 1 = Reset AWD and restart timeout period. * 0 = No effect.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
RUN Mode During RUN mode the main voltage regulator is on. It provides a regulated supply to all digital sections. STOP Mode During STOP mode the STOP mode regulator supplies a regulated output voltage. The STOP mode regulator has a very limited output current capability. The output voltage will be lower than the output voltage of the main voltage regulator.
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E625, various parameters (e.g. ICG trim value) are stored in the flash memory of the device. The following flash memory locations are reserved for this purpose and might have a value different from the "empty" (0xFF) state: * 0xFD800xFDDF Trim and Calibration Values * 0xFFFE:0xFFFF Reset Vector In the event the application uses these parameters, one has to take care not to erase or override these values. If these parameters are not used, these flash locations can be erased and otherwise used.
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PACKAGE THERMAL PERFORMANCE
Figure 21 shows a thermal response curve for a package mounted onto a thermally enhanced PCB. Note The PCB board is a multi-layer with two inner copper planes (2s2p). The board conforms to JEDEC EIA/JESD 51-5 and JESD51-7. Substrate thickness is 1.60 mm. Top and bottom copper trace layers are 0.7 mm thick, with two inner copper planes of 0.35 mm thickness. Thermal vias have 0.35 mm thick plating.
Thermal Impedance [C/W]
30 25 20 15 10 5 5.0 0 0.00001 0.0001
Thermal Impedance (C/W)
0.001
0.01
0.1 1 1.0 Time (s)
10
100
1000
10000
time[s]
Figure 21. Thermal Response of H-Bridge Driver with Package Soldered to a JEDEC PCB Board
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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908E625 37
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PACKAGE DIMENSIONS
DWB SUFFIX 54-TERMINAL SOIC WIDE BODY EXPOSED PAD PLASTIC PACKAGE CASE 1400-01 ISSUE B
10.3 5 7.6 7.4 C 9 B 2.65 2.35
52X 54
1
0.65
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PIN 1 INDEX
4 9 B B 18.0 17.8 C L
27
28
5.15
2X 27 TIPS
A
54X
SEATING PLANE
0.3
ABC
0.10 A
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF HTE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTOM OF THE PLASTIC BODY.
A R0.08 MIN C A 8 0 0.9 0.5 0.1 0.0 SECTION B-B C 0.25
GAUGE PLANE
0MIN
(1.43)
10.9 9.7 0.30 A B C
(0.29) 0.30 0.25 0.38 0.22 0.13
M
BASE METAL
5.3 4.8 0.30 A B C
(0.25)
6
PLATING
A BC
8
SECTION A-A
ROTATED 90 CLOCKWISE
VIEW C-C
908E625 38
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
NOTES
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product, Go to: www.freescale.com
908E625 39
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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective owners. (c) Motorola, Inc. 2004
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405, Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors
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